1. Field of the Invention
The invention generally relates to the design verification of integrated circuits (ICs) and more specifically to a verification flow that optimizes the verification of large ICs by using a hierarchical approach to clock-domain crossing (CDC) verification.
2. Description of the Related Art
Today's integrated circuits (ICs) are getting ever larger with millions upon millions of transistors integrated in a single IC that is in fact a system on chip (SoC). As part of the verification of a design it is necessary to verify that signals crossing clock domains operate properly. Often a single clock-domain crossing (CDC) verification run of a large IC takes several days. This makes it very hard to perform multiple runs needed to successfully close CDC verification, and to integrate the runs into a regression flow.
Prior art, such as SpyGlass® CDC, a product of Assignee, provides an IP Block constraint approach for hierarchical CDC verification of large designs. This constraint hides the details of the block on which it is applied except for its input/output interface. A similar approach is provided by Kwok in US patent application 20100242003 where partitioning into blocks is suggested, where a block level clock-domain crossing verification process is performed on selected blocks. Verification interface files are then generated by the block level clock domain crossing process. Then, a top level clock domain crossing verification process is performed over the entire design. While this approach is effective for verifying the correctness of the domains on the interface between the block and the SoC, it does not address various other requirements for complete CDC verification. One requirement is that a constant value on the output of a block must have a corresponding constant value on the corresponding input at the SoC level. Another requirement is that a control synchronizer in one block does not converge with a control synchronizer from another block at a gate outside these blocks. In summary, previous solutions lacked a holistic abstraction scheme that addresses all the needs of complete CDC verification. As a result, design teams avoid the use of these flows and resort to verification at the SoC level without using a hierarchical flow. This made the CDC verification of even smaller-sized SoCs a challenge, especially when multiple iterations are necessary to fix identified problems.
As the prior art suffers from deficiencies that make it incomplete with respect to a hierarchical verification of CDC, there is a need in the art to resolve such deficiencies. In particular it would be advantageous to provide a solution for hierarchical CDC verification that would practically allow repeated verification cycles without the high burden associated with repeated runs at the SoC level and incomplete results with IP Block constraints.